The invention relates to integrated circuit packaging, particularly to mounting of chip and formation of interconnections, and more particularly to a repairable chip bonding/interconnection process.
Various processes have been developed for the packaging of integrated circuits involving securing bare (unencapsulated) chips to a substrate and forming desired interconnects on the chips and substrate. The problems associated with the formation of lead lines or interconnects on the vertical surfaces of chips and/or substrates has been substantially reduced by a technology generally known as laser pantography or laser direct-writing, wherein the laser is rastered with computer control to form the pattern from data stored as a computer file. Thus, the laser beam can be manipulated to any appropriate surface, either horizontal, vertical or at an angle through the use of computer controlled optics and stages (either an angled beam or a tilted stage is utilized). The laser is not used simply as a light source that shines through a mask as in conventional lithography, but is focused to the required size to form the desired pattern on a chip or substrate. Various fabrication techniques using laser pantography have been recently developed by David D. Tuckerman and others, such as exampled by U.S. Pat. No. 4,992,847 issued Feb. 12, 1991.
Repairability of chip-to-board interconnection has long been a problem in the packaging of integrated circuits onto multichip modules, particularly chip-to-board interconnects which provide for testability without destruction of the chips and/or board. The present invention is directed to a resolution of this problem, and involves a repairable chip-to-board interconnect technique which addresses cost and testability issues. The invention involves a chip-on-sacrificial-substrate approach. The invention includes the formation of transmission lines from the chip to temporary board or substrate which end in gull wing interconnects at the bottom of the chip for subsequent bonding to a substrate or circuit board at a point of use. The invention provides for testability after the "gull wing" interconnects are formed, but before dissolution of the sacrificial substrate or layer, whereby the chip can be tested at speed and burned in. If good, the chip can then be removed from the sacrificial substrate and bonded to a permanent substrate.